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Intel and Micron’s joint venture IMFT has announced that it has produced a 128Gb die. A package combining eight such dies together would be small enough to fit on a fingertip and boast an unprecedented 128GB capacity. Mass production will start in the first half of next year, and devices using the new dies are likely to start shipping in 2013.
IMFT also announced that it had started mass production of a 64Gb 20nm die. This part was first announced in April of this year. Consumer delivery should start in the middle of next year.
The 128Gb parts will take longer to reach consumers because in addition to having a larger capacity, they also include a new interface and page size. NAND flash dies are organized internally into pages, and pages are organized into blocks. Read and write operations occur a page at a time; erase operations have to be performed a block at a time.
Current flash chips, including the 64Gb parts that IMFT has started mass producing, use a page size of 8,192 bytes. The 128Gb dies increase this to 16,384 bytes. As a result, controllers and drive firmware will have to be modified to accommodate the new page size.
Flash chips used today use an interface called ONFi 2.x. This specifies a maximum of 200 megatransfers per second (MT/s) per controller channel. The 128Gb parts use ONFi 3, which increases the maximum to 333 MT/s. Just as with the increased page size, this will require controllers and firmware to be updated.
Together, these factors mean that the 128Gb parts are not merely scaled up versions of the 64Gb parts, and so the design and testing of flash drives that use them will be more complicated.
Beyond capacity and speed, another important property of flash memory is endurance; the number of times each block can be erased before it fails. Both the 64Gb and 128Gb dies use multi-level cell (MLC) technology. With MLC, each individual flash cell (the smallest flash unit, responsible for storing just a single value) can be set to one of several different values—in most cases, four different values, equivalent to two bits, though Samsung is sampling three bit cells. The alternative is single-level cells (SLC), where each cell can hold only a single bit. MLC allows greater density—a given number of cells stores more bits—but tends to come at some cost in endurance. MLC flash typically withstands a few thousand erasures, whereas SLC can tolerate tens of thousands.
Die shrinks also tend to reduce endurance, with old 65 m MLC flash being rated at 5,000-10,000 erase cycles, but that number dropping to 3,000-5,000 for 25nm MLC flash. However, IMFT is claiming that the shrink to 20nm has not caused any corresponding reduction in endurance. Its 20nm flash uses a Hi-K/metal gate design which allows it to make transistors that are smaller but no less robust. IMFT is claiming that this use of Hi-K/metal gate is a first for NAND flash production.
When the chips using the new dies do eventually hit the market, they should enable standard 2.5″ drives to hold up to 2 TB, and the smaller memory stick format used in Ultrabooks and the MacBook Air to hold up to 1 TB.